B. VAMSI KRISHNA; BOTTA. CHAKRADHAR; S. NAGARAJ; DR.P.K. ANAND PREM. ANALYSIS OF VEDIC MULTIPLIER FOR CONVENTIONAL CMOS, COMPLEMENTARY PASS TRANSISTOR LOGIC (CPL) & DOUBLE PASS TRANSISTOR LOGIC (DPL) LOGICS. PalArch’s Journal of Archaeology of Egypt / Egyptology, [S. l.], v. 17, n. 7, p. 5649–5656, 2020. Disponível em: https://archives.palarch.nl/index.php/jae/article/view/2737. Acesso em: 3 nov. 2025.