B. Vamsi Krishna, Botta. Chakradhar, S. Nagaraj, and Dr.P.K. Anand Prem. “ANALYSIS OF VEDIC MULTIPLIER FOR CONVENTIONAL CMOS, COMPLEMENTARY PASS TRANSISTOR LOGIC (CPL) &Amp; DOUBLE PASS TRANSISTOR LOGIC (DPL) LOGICS”. PalArch’s Journal of Archaeology of Egypt / Egyptology, vol. 17, no. 7, Nov. 2020, pp. 5649-56, https://archives.palarch.nl/index.php/jae/article/view/2737.