An Efficient Architecture for 8-point Discrete Cosine Transform using Less Number of Multipliers

Abstract

In this paper, a simple architecture has been presented for direct implementation of 8-point discrete
cosine transform (DCT). This architecture is suitable for VLSI implementation and it provides high
throughput of computation. Since the architecture uses minimum number of multipliers, its area-and
hardware-complexities are less. Its VLSI performance is good. Sub expression sharing technique and
sharing the multipliers with same constants have been used in this architecture.