ANALYSIS OF VEDIC MULTIPLIER FOR CONVENTIONAL CMOS, COMPLEMENTARY PASS TRANSISTOR LOGIC (CPL) & DOUBLE PASS TRANSISTOR LOGIC (DPL) LOGICS

Abstract

In this work we have designed and analyse Vedic Multiplier for conventional CMOS, Complementary Pass Transistor Logic (CPL) & Double pass transistor logic (DPL). Vedic Multiplier is designed for 4-bit using conventional CMOS gates, CPL gates and DPL gates. Their Speed, Area and Power is analysed and compared. The design is implemented using t HSPICE for 180nm Technology.